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INTEGRATED CIRCUITS
PCK2023 CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
Product data File under Integrated Circuits -- ICL03 2001 Sep 07
Philips Semiconductors
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
FEATURES
* 3.3 V operation * Three differential CPU clock pairs * Ten PCI clocks at 3.3 V * Six 66 MHz clocks at 3.3 V * Two 48 MHz clocks at 3.3 V * One 14.318 MHz reference clock * 66,100, 133 or 200 MHz operation * Power management control pins * CPU clock skew less than 200 ps cycle-to-cycle * CPU clock skew less than 150 ps pin-to-pin * 1.5 ns to 3.5 ns delay on PCI pins * Spread Spectrum capability
DESCRIPTION
The PCK2023 is a clock synthesizer/driver for a Pentium IV and other similar processors. The PCK2023 has three differential pair CPU current source outputs. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. There are six 3V66 outputs. Finally, there is one 3.3 V reference clock at 14.318 MHz. All clock outputs meet Intel's drive strength, rise/fall times, jitter, accuracy, and skew requirements. The part possesses a dedicated power-down input pin for power management control. This input is synchronized on-chip and ensures glitch-free output transitions.
PIN CONFIGURATION
VDD 1 XTAL_In XTAL_Out VSS PCIF0 PCIF1 PCIF2 VDD VSS 2 3 4 5 6 7 8 9 56 REF_0 55 S0 54 CPU3 53 CPU3 52 CPU0 51 CPU0 50 VDD 49 CPU1 48 CPU1 47 VSS 46 VDD 45 CPU2 44 CPU2 43 Mult0 42 IREF 41 VSS Iref 40 S2 39 USB 48 MHz 38 DOT 48 MHz 37 VDD 48 MHz 36 VSS 48 MHz 35 3V66_1/VCH 34 PCI_Stop 33 3V66_0 32 VDD 31 VSS 30 SCLK 29 SDATA
PCI0 10 PCI1 11 PCI2 12 PCI3 13 VDD 14 VSS 15 PCI4 16 PCI5 17 PCI6 18 VDD 19 VSS 20 66Buff0/3V66_2 21 66Buff1/3V66_3 22 66Buff2/3V66_4 23 66In/3V66_5 24 PWRDWN 25 VDDA 26 VSSA 27 Vtt_Pwrgd 28
SW00695
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP 56-Pin Plastic TSSOP TEMPERATURE RANGE 0 to +70 C 0 to +70 C ORDER CODE PCK2023DL PCK2023DGG DRAWING NUMBER SOT371-1 SOT364-1
Intel and Pentium are registered trademarks of Intel Corporation.
2001 Sep 07
2
853-2278 27052
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
PIN DESCRIPTION
PIN NUMBER 56 2 3 44, 45, 48, 49, 51, 52 33 35 24 21, 22, 23 5, 6, 7 10, 11, 12, 13, 16, 17, 18 39 38 40 54, 55 42 43 25 34 53 28 29 30 1, 8, 14, 19, 32, 37, 46, 50 26 4, 9, 15, 20, 31, 36, 41, 47 27 SYMBOL ref XTAL_In XTAL_Out CPU & CPU [2:0] 3V66_0 3V66_1/VCH 66In/3V66_5 66Buff [2:0] / 3V66 [4:2] PCIF [2:0] PCI [6:0] USB DOT S2 S1, S0 Iref Mult0 PWRDWN PCI_Stop CPU_Stop Vtt_Pwrgd SDATA SCLOCK VDD VDDA VSS VSSA 3.3 V 14.318 MHz clock output. 14.318 MHz crystal input. 14.318 MHz crystal output. Differential CPU clock outputs. 3.3 V 66 MHz clock output. 3.3 V selectable through I2C to be 66 MHz or 48 MHz 66 MHz input to buffered 66Buff and PCI or 66 MHz clock from internal VCO. 66 MHz buffered outputs from 66 input or 66 MHz clocks from internal VCO. 33 MHz clocks divided down from 66 input or divided down from 3V66. PCI clock outputs divided down from 66 input or divided down from 3V66. Fixed 48 MHz clock output. Fixed 48 MHz clock output. Special 3.3 V 3 level input for mode selection. 3.3 V LVTTL inputs for CPU frequency selection. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3 V LVTTL input for selecting the current multiplier for the CPU outputs. 3.3 V LVTTL input for PowerDown active low. 3.3 V LVTTL input for PCI_Stop active low. 3.3 V LVTTL input for CPU_Stop active low. 3.3 V LVTTL input is a level sensitive strobe used to determine when S [2:0] and Mult0 inputs are valid and ok to be sampled (active low). I2C compatible SDATA. I2C compatible SCLOCK. 3.3 V power supply for outputs. 3.3 V power supply for PLL. Ground for outputs. Ground for PLL. FUNCTION
2001 Sep 07
3
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
BLOCK DIAGRAM
PWRDWN
X
REF [0](14.318 MHz)
XIN X 14.318 MHZ OSC
USBPLL
PWRDWN
X
DOT/USB 48 MHz
XOUT X
PWRDWN SYSPLL PWRDWN IREF X PWRDWN IBIAS
X 3V66_1/VCH(48/66 MHz)
X
CPU [0-2](100/133 MHz)
X CPU [0-2](100/133 MHz)
PWRDWN
X
3V66 [2-4] (66 MHz)
CPU STOP X PCI STOP X PWRDWN X S2 X S1 X S0 X MULT0 X Vtt Pwrgd X SDA X SCL X X PCIF [0-2] (33 MHz) PWRDWN X PCI [0-6](33 MHz) LOGIC PWRDWN X 3V66_0 (66 MHz) PWRDWN X 66ln/3V66_5(66 MHz)
SW00861
2001 Sep 07
4
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
FREQUENCY SELECT/FUNCTION TABLE
S2 1 1 1 1 0 0 0 0 Mid Mid S1 0 0 1 1 0 0 1 1 0 0 S0 0 1 0 1 0 1 0 1 0 1 CPU 66 MHz 100 MHz 200 MHz 133 MHz 66 MHz 100 MHz 200 MHz 133 MHz Low Tclk/2 3V66 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz Hi Z Tclk/4 66BUFF/ 3V66 66 In 66 In 66 In 66 In 66 MHz 66 MHz 66 MHz 66 MHz Hi Z Tclk/4 66In/ 3V66_5 66 input 66 input 66 input 66 input 66 MHz 66 MHz 66 MHz 66 MHz Hi Z Tclk/4 PCIF/PCI 66 In/2 66 In/2 66 In/2 66 In/2 33 MHz 33 MHz 33 MHz 33 MHz Hi Z Tclk/8 REF 0 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz Hi Z Tclk USB/DOT 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz Hi Z Tclk/2 3V66_1/ VCH 66/48 MHz 66/48 MHz 66/48 MHz 66/48 MHz 66/48 MHz 66/48 MHz 66/48 MHz 66/48 MHz Hi-Z Tclk/4
NOTE: 1. Mid is defined as a voltage level between 1.0 V and 1.8 V for 3 level input functionality. Low is below 0.8 V. High is above 2.0 V. 2. 3V66_1/VCH output frequency is set by the I2C. 3. Frequency of the 48 MHz outputs must be +167 ppm to match USB default. 4. Rref output min = 14.316 MHz, nominal = 14.31818, max = 14.32 MHz. 5. Tclk is a test clock over-driven on the XTAL_In input during test mode.
POWER DOWN MODE
PWRDWN 1 0 CPU Normal Iref*2 CPU Normal Float 3V66 Normal Low 66BUFF/ 3V66 Normal Low 66In/ 3V66_5 Normal Low PCIF/PCI Normal Low REF 0 Normal Low USB/DOT Normal Low 3V66_1/ VCH Normal Low
HOST SWING SELECT FUNCTIONS - CK408
MULT 0 0 1 BOARD IMPEDANCE 50 50 Iref Rref = 221.1% Iref = 5.00 mA Rref = 475.1% I ref = 2.32 mA LOAD Nominal test load for given configuration Nominal test load for given configuration IOH IOH = 4*Iref IOH = 6*Iref VOH @ 50 W 1.0 V 0.7 V
CONDITIONS IOUT IOUT VDD = 3.3 V VDD = 3.3 V 5%
CONFIGURATION All combinations, see Table above All combinations, see Table above
MIN. -7% of IOH See Table above -12% of IOH See Table above
MAX. +7% of IOH See Table above +12% of IOH See Table above
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VDD3 IIK VI IOK VO IO Tstg Ptot PARAMETER DC 3.3 V supply DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current Storage temperature range Power dissipation per package plastic medium-shrink (SSOP) For temperature range: -40 to +125C above +55C derate linearly with 11.3 mW/K VI < 0 Note 2 VO > VDD or VO < 0 Note 2 VO = 0 to VDD CONDITION LIMITS MIN -0.5 -- -- -- -0.5 -- -65 -- MAX +4.6 -50 -- 50 VDD + 0.5 50 +150 850 UNIT V mA V mA V mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC OPERATING CONDITIONS
SYMBOL VDD3 AVDD VIH VIL VOL3 VOH3 IIL fref CIN CXTAL COUT LPIN Tamb PARAMETER DC 3.3 V supply voltage DC 3.3 V analog supply voltage 3.3 V input high voltage 3.3 V input high voltage 3.3 V input low voltage 3.3 V input high voltage Input leakage current reference frequency, oscillator normal value Input pin capacitance Xtal pin capacitance Output pin capacitance Pin inductance Operating ambient temperature range in free air IOL = 1.0 mA IOH = 1.0 mA 0 < VIN < VDD CONDITIONS LIMITS MIN 3.135 3.135 2.0 VSS - 0.3 -- 2.4 -5 14.31818 -- 13.5 -- -- 0 MAX 3.465 3.465 VDD + 0.3 0.8 0.4 -- +5 14.31818 5 22.5 6 7 +70 UNIT V V V V V V A MHz pF pF pF nH C 2 3 2 2 1 NOTES
NOTES: 1. Input leakage current does not include inputs with pull up or pull down resistors. 2. This is a recommendation, not an absolute requirement. 3. As seen by the crystal. Device is intended to be used with a 17-20 pF AT crystal.
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
POWER MANAGEMENT
CONDITION Power-down mode (PWRDWN = 0) Full active MAXIMUM 3.3 V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDDL= 3.465 V ALL STATIC INPUTS = VDD3 OR VSS 25 mA @ Iref = 2.32 mA 46 mA @ Iref = 5.0 mA 280 mA
CPU STOP FUNCTIONALITY
CPU_STOP 1 0 CPU Normal Iref*2 CPU Normal Float 3V66 66 MHz 66 MHz 66BUFF 66 input 66 input PCIF/PCI 66 input/2 66 input/2 USB/DOT 48 MHz 48 MHz
DC CHARACTERISTICS
SYMBOL PARAMETER VDD (V) IO OH IO OL IO OH IO OL IO OH IO OL VOL II IOZ 48 MHz USB, VCH USB 48 MHz USB, VCH USB 48 MHz DOT 48 MHz DOT REF, PCI, PCIF, , , , 3V66, 66BUFF REF, PCI, PCIF, , , , 3V66, 66BUFF CPU/CPU Input leakage current 3-State output OFF-State current 3.135 3.465 3.135 3.465 3.135 3.465 3.135 3.465 3.135 3.465 3.135 3.465 VSS = 0.0 3.365 3.465 TEST CONDITIONS OTHER VOUT = 1.0 V VOUT = 3.135 V VOUT = 1.95 V VOUT = 0.4 V VOUT = 1.0 V VOUT = 3.135 V VOUT = 1.95 V VOUT = 0.4 V VOUT = 1.0 V VOUT = 3.135 V VOUT = 1.95 V VOUT = 0.4 V RS = 33.2 RP= 49.9 0 < VIN < VDD3 VOUT = VDD or GND Type 3A y 12-60 Type 3A y 12-60 Type 3B y 12-60 Type 3B y 12-60 Type 5 y 12-55 Type 5 y 12-55 Type X1 -- IO = 0 LIMITS Tamb = 0 to +70 C MIN -29 -- 29 -- -29 -- 29 -- -33 -- 30 -- 0.0 -5 -- TYP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX -- -23 -- 27 -- -23 -- 27 -- -33 -- 38 0.05 5 10 mA mA mA mA mA mA V A A UNIT
NOTE: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section.
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
AC CHARACTERISTICS
VDD3 = 3.3 V -5%; fcrystal = 14.31818 MHz
3V66 66 MHz TIMING REQUIREMENTS
SYMBOL TPERIOD tHIGH tLOW tRISE tFALL tJITTER Edge rate Edge rate tSKEW tSKEW tSKEW PARAMETER period HIGH time LOW time rise time fall time cycle-to-cycle jitter rising edge rate falling edge rate pin-to-pin skew 3V66 [1:0] pin-to-pin skew 3V66 [5:2] pin-to-pin skew 3V66 [5:0] LIMITS Tamb = 0 to +70 C MIN 15.0 4.95 4.55 0.5 0.5 -- 1.0 1.0 0.0 0.0 0.0 MAX 15.3 N/A N/A 2.0 2.0 250 4.0 4.0 250 250 450 ns ns ns ns ns ps V/ns V/ns ps ps ps 12 12 8, 13 9 10 12 12 UNIT NOTES
66 MHz BUFFERED TIMING REQUIREMENTS
SYMBOL tRISE tFALL tPD Edge rate Edge rate tSKEW PARAMETER rise time fall time propagation delay from 66In to 66BUFF [2:0] rising edge rate falling edge rate 66 MHz buffered pin-to-pin skew LIMITS Tamb = 0 to +70 C MIN 0.5 0.5 2.5 1.0 1.0 0.0 MAX 2.0 2.0 4.5 4.0 4.0 175 ns ns ns V/ns V/ns ps 12 12 12 12 UNITS NOTES
PCIF/PCI AC TIMING REQUIREMENTS
SYMBOL TPERIOD tHIGH tLOW tRISE tFALL tJITTER Edge rate Edge rate tSKEW tPCI PARAMETER period HIGH time LOW time rise time fall time cycle-to-cycle jitter rising edge rate falling edge rate pin-to-pin skew 3V66 [5:0] leads 33 MHz PCI LIMITS Tamb = 0 to +70 C MIN 30.0 12.0 12.0 0.5 0.5 -- 1.0 1.0 0.0 1.5 MAX N/A N/A N/A 2.0 2.0 -- 4.0 4.0 500 3.5 ns ns ns ns ns ps V/ns V/ns ps ns 12 12 8, 13 9 10 12 12 UNITS NOTES
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
USB 48 MHz AC TIMING REQUIREMENTS
SYMBOL TPERIOD (average) tHIGH tLOW f tRISE tFALL tJITTER Edge rate Edge rate PARAMETER period HIGH time LOW time frequency rise time fall time cycle-to-cycle jitter rising edge rate falling edge rate LIMITS Tamb = 0 to +70 C MIN 8.094 7.694 48.000 1.0 1.0 0 1.0 1.0 MAX ns ns ns MHz ns ns ps V/ns V/ns 8 12 12 10.036 9.836 48.008 2.0 2.0 350 2.0 2.0 nominal = 20.829 UNITS NOTES
DOT 48 MHz AC TIMING REQUIREMENTS
SYMBOL TPERIOD (average) tHIGH tLOW f tRISE tFALL tJITTER Edge rate Edge rate tSKEW PARAMETER period HIGH time LOW time frequency rise time fall time cycle-to-cycle jitter rising edge rate falling edge rate USB to DOT LIMITS Tamb = 0 to +70 C MIN 8.094 7.694 48.000 0.5 0.5 -- 2.0 2.0 -- MAX ns ns ns MHz ns ns ps V/ns V/ns ps 8 12 12 10.036 9.836 48.008 1.0 1.0 350 4.0 4.0 1000 nominal = 20.829 UNITS NOTES
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
CPU 0.7 V AC TIMING REQUIREMENTS
CPU 200 MHz SYMBOL TPERIOD tABSMIN tRISE tFALL tRISE tFALL PARAMETER average period absolute minimum host clock period rise time fall time rise time variation fall time variation absolute crossing point voltages total variation of VCROSS for rising edge of host total variation of VCROSS over all edges cycle-to-cycle jitter MIN 5.0 4.8 175 175 -- -- MAX 5.1 -- 600 600 150 150 CPU 133 MHz MIN 7.5 7.3 175 175 -- -- MAX 7.65 -- 600 600 150 150 CPU 100 MHz MIN 10.0 9.8 175 175 -- -- MAX 10.2 -- 600 600 150 150 CPU 66 MHz MIN 15.0 14.8 175 175 -- -- MAX 15.3 -- 600 600 150 150 UNITS ns ns ps ps ps ps NOTES 1, 7 1, 7 2, 7, 14 2, 7, 14 2, 7 2, 7
VCROSS
280
430
280
430
280
430
280
430
mV
7
VCROSS
--
90
--
90
--
90
--
90
mV
3, 7
Total VCROSS tCCJITTER Duty Cycle
--
110
--
110
--
110
--
110
mV
4, 7
-- 45
150 55
-- 45
150 55
-- 45
150 55
-- 45
150 55
ps %
7, 15 7
Overshoot
maximum voltage allowed at output minimum voltage allowed at output pin-to-pin
--
850
--
850
--
850
--
850
mV
7
Undershoot
--
-150
--
-150
--
-150
--
-150
mV
7
tSKEW
--
150
--
150
--
150
--
150
ps
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
CPU 1.0 V AC TIMING REQUIREMENTS
CPU 200 MHz SYMBOL TPERIOD tABSMIN Diff-tRISE Diff-tFALL PARAMETER average period absolute minimum host clock period rise time fall time Absolute single-ended rise/fall waveform symmetry absolute crossing point voltages cycle-to-cycle jitter -- maximum voltage allowed at output minimum voltage allowed at output rising edge ringback falling edge ringback MIN 5.0 4.85 175 175 MAX 5.1 -- 467 467 CPU 133 MHz MIN 7.5 7.35 175 175 MAX 7.65 -- 467 467 CPU 100 MHz MIN 10.0 9.85 300 175 MAX 10.2 -- 467 467 CPU 66 MHz MIN 15.0 14.85 300 175 MAX 15.3 -- 467 467 UNITS ns ns ps ps NOTES 1, 15 1, 15 15, 16 15, 16
SE SKEW
--
325
--
325
--
325
--
325
ps
17, 18
VCROSS tCCJITTER Duty Cycle
0.51
0.76
0.51
76
0.51
76
--
--
V
18
-- 45
150 55
-- 45
150 55
-- 45
150 55
-- 45
150 55
ps %
15, 19 15
SE-VOH
.92
1.45
.92
1.45
.92
1.45
.92
1.45
V
18
SE-VOL DiffVRING_RISE DiffVRING_FALL
-200
350
-200
350
-200
350
-200
350
mV
18
0.35 --
-- -0.35
0.35 --
-- -0.35
0.35 --
-- -0.35
0.35 --
-- -0.35
V V
15 15
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
ALL OUTPUTS
SYMBOL tPZL/tPZH tPZL/tPZH tSTABLE PARAMETER output enable delay (all outputs) output disable delay (all outputs) all clock stabilization from power-up LIMITS Tamb = 0 to +70 C MIN 1.0 1.0 -- MAX 10.0 10.0 3 ns ns ms 11 UNITS NOTES
NOTES: 1. Measured at crossing points or where subtraction of CLK-CLK crosses 0 V. 2. Measured from VOL = 0.175 V to VOH = 0.525 V. 3. These crossing points refer to only crossing points containing a rising edge of a CPU output (as opposed to a CPU output). 4. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. 5. Measured from VOL = 0.2 V to VOH = 0.8 V. 6. Determined as a fraction of 2* (tRISE-tFALL)/(tRISE+tFALL). 7. Test load is RS = 33.2 , RP = 49.9 . 8. Period, jitter, offset and skew measured at rising edge @ 1.5 V for 3.3 V clocks. 9. THIGH is measured at 2.4 V for non-CPU outputs. 10. TLOW is measured at 0.4 V for all outputs. 11. The time specified is measured from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable and operating within specification. 12. The 3.3 V clock tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification. 13. The average period over any 1 s period of time must be greater than the minimum specified period. 14. Designed for 150-420 ps (1 V/ns minimum rise time across 0.42 V). 15. Measurement taken from differential waveform. 16. Measurement taken from differential waveform from -0.35 to +0.35 V. 17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86 V. Rise/fall time matching is defined as "the instantaneous difference between maximum CLK rise (fall) and minimum CLK fall (rise) time, or minimum CLK rise (fall) and maximum CLK fall (rise) time". This parameter is designed for waveform symmetry. 18. Measured in absolute voltage, single ended. 19. Cycle-to-cycle jitter measurements taken with minimum capacitive loading on non-CPU outputs.
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
AC WAVEFORMS
VM = 1.25 V @ VDDL and 1.5 V @ VDD3 VX = VOL + 0.3 V VY = VOH - 0.3 V VOL and VOH are the typical output voltage drop that occur with the output load.
VI SEL1, SEL0 GND tPLZ tPZL VM
VOH 50% HOST CLK VSS
VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL VM VX tPHZ VOH tPZH
VOH HOST CLK 50% VSS tSKEW tPERIOD
OUTPUT HIGH-to-OFF OFF-to-HIGH VSS Outputs enabled
VY VM
SW00850
Outputs disabled
Outputs enabled
SW00571
Figure 1. Host clock Figure 3. State enable and disable times
COMPONENT MEASUREMENT POINTS VOH = 2.4 V
VOL = 0.4 V VSS
VDDL VIH = 2.0 V 1.5 V VIL = 0.7 V SYSTEM MEASUREMENT POINTS
SW00851
Figure 2. 3.3 V clock waveforms
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
S1 VDD 2 VDD Open VSS 500 VI PULSE GENERATOR D.U.T. CL RT VO
500
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2 VDD VSS
VDD = VDDL or VDD3, DEPENDS ON THE OUTPUT
SW00852
Figure 4. Load circuitry for switching times
PWRDWN
HOST CLK (INTERNAL)
PCICLK (INTERNAL)
PWRDWN
HOST CLK (EXTERNAL) PCICLK (EXTERNAL) OSC & VCO
USB (48 MHz)
Figure 5. Power management
2001 Sep 07
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AA AA AA AA
SW00853
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
POWER-UP SEQUENCE
Figure 6 shows the power-up sequence for the PCK2023. Once power is applied to the device, an internal sense circuit generates a signal when the supply is above approximately 2 volts. This signal generates a series of timed signals that control the sequential event inside the device. First, the multifunction pins are latched into the device. These latched signals are then used to define the mode of operation of the device. A short time later, the PLL is enabled and begins running. After XX ms, the clock outputs are enabled and begin running
INTERNAL 3.3 V SUPPLY
INTERNAL POWER GOOD
SIGNAL LATCH
OPERATING MODE SET/PLL START
OUTPUTS ENABLED
SW00854
Figure 6. Power-up sequence
VDD CL RP = 500
RS HOST CRYSTAL 14.318 MHz DUT HOST RS RS = 33.2
RP = 50
SW00855
Figure 7. Host clock measurements
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
TPKP DUTY CYCLE TPKH 3.3 V CLOCKING INTERFACE 2.4 V 1.5 V 0.4 V TPKL TRISE TFALL
SW00856
Figure 8. 3.3 V clock waveforms
2001 Sep 07
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
I2C SPECIFICATION
1
2
3
4
5
6
7
8
9 DUMMY BYTE 1
SLAVE ADDRESS
DUMMY BYTE 2
S
1
1
0
1
0
0
1
0
AS
0
0
0
0
0
0
0
0
AS
0
0
0
0
0
0
0
0
AS
BYTE 0
AS
START CONDITION
R/W
SLAVE ACKNOWLEDGE
SLAVE ACKNOWLEDGE
SLAVE ACKNOWLEDGE
SLAVE ACKNOWLEDGE
BYTE 1
AS
BYTE 2
AS SLAVE ACKNOWLEDGE
BYTE 3
AS SLAVE ACKNOWLEDGE
BYTE 4
AS
SLAVE ACKNOWLEDGE
SLAVE ACKNOWLEDGE
BYTE 5
AS
BYTE 6
AS
P STOP CONDITION
SLAVE ACKNOWLEDGE
SLAVE ACKNOWLEDGE
SW00848
Figure 9. I2C write
1
2
3
4
5
6
7
8
9 BYTE COUNT BYTE (ALWAYS 8)
SLAVE ADDRESS
S
1
1
0
1
0
0
1
1
AS
0
0
0
0
0
1
1
0
AM
BYTE 0
AM MASTER ACKNOWLEDGE
BYTE 1
AM
START CONDITION
R/W
SLAVE ACKNOWLEDGE
MASTER ACKNOWLEDGE
MASTER ACKNOWLEDGE
BYTE 2
AM
BYTE 3
AM
BYTE 4
AM
BYTE 5
AM
MASTER ACKNOWLEDGE
MASTER ACKNOWLEDGE
MASTER ACKNOWLEDGE
MASTER ACKNOWLEDGE
BYTE 6
AM
P STOP CONDITION
MASTER ACKNOWLEDGE
SW00849
Figure 10. I2C read
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Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
BYTE 0
BIT 0 DESCRIPTION/FUNCTION S0 reflects the value of the Sel_0 pin sampled on power-up S1 reflects the value of the Sel_1 pin sampled on power-up S2 reflects the value of the Sel_2 pin sampled on power-up PCI_stop. This bit is ANDed with the PCI_STOP pin for I2C readback and control of PCI outputs CPU_stop reflects the current value of the external CPU_Stop pin VCH select 66 MHz/48MHz enabled not used spread spectrum enabled TYPE R POWER UP CONDITION externally selected OUTPUT(S) AFFECTED N/A PIN AFFECTED N/A SOURCE PIN 54
1
R
externally selected
N/A
N/A
55
2
R
externally selected
N/A
N/A
40
3
RW
externally selected
All PCI clock outputs except PCI[2:0] pins All CPU clock pairs
10, 11, 12, 13, 16, 17, 18
34
4
R
externally selected
44, 45, 48, 49, 51, 52 35 -- 5, 6, 7, 10, 11, 12, 13, 16, 17, 18, 33, 35
53
5 6 7
RW -- RW
0 = 66MHz enabled 0 0 = spread off
3V66_1/VCH -- CPU[2:0], 3V66[1:0]
N/A -- N/A
BYTE 1
BIT 0 DESCRIPTION/FUNCTION CPU0 output enable 1 = enabled 0 = disabled CPU1 output enable 1 = enabled 0 = disabled CPU2 output enable 1 = enabled 0 = disabled allow control of CPU0 with assertion of CPU_Stop 1 = enabled 0 = disabled allow control of CPU1 with assertion of CPU_Stop 1 = enabled 0 = disabled allow control of CPU2 with assertion of CPU stop 1 = enabled 0 = disabled not used CPU Mult0 value sampled at startup TYPE RW POWER UP CONDITION 1 = enabled OUTPUT(S) AFFECTED CPU0 CPU0 CPU1 CPU1 CPU2 CPU2 CPU0 CPU0 PIN AFFECTED 51, 52 SOURCE PIN N/A
1
RW
1 = enabled
48, 49
55
2
RW
1 = enabled
44, 45
40
3
RW
0 = not free running, is affected by CPU_Stop 0 = not free running, is affected by CPU_Stop 0 = not free running, is affected by CPU_Stop 0 externally selected
51, 52
34
4
RW
CPU1 CPU1
48, 49
53
5
RW
CPU2 CPU2
44, 45
N/A
6 7
-- R
-- N/A
-- N/A
-- 43
2001 Sep 07
18
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
BYTE 2
BIT 0 DESCRIPTION/FUNCTION PCI0 output enabled 1 = enabled 0 = disabled PCI1 output enabled 1 = enabled 0 = disabled PCI2 output enabled 1 = enabled 0 = disabled PCI3 output enabled 1 = enabled 0 = disabled PCI4 output enabled 1 = enabled 0 = disabled PCI5 output enabled 1 = enabled 0 = disabled PCI6 output enabled 1 = enabled 0 = disabled not used TYPE RW POWER UP CONDITION 1 = enabled OUTPUT(S) AFFECTED PCI0 PIN AFFECTED 10 SOURCE PIN N/A
1
RW
1 = enabled
PCI1
11
N/A
2
RW
1 = enabled
PCI2
12
N/A
3
RW
1 = enabled
PCI3
13
N/A
4
RW
1 = enabled
PCI4
16
N/A
5
RW
1 = enabled
PCI5
17
N/A
6
RW
1 = enabled
PCI6
18
N/A
7
--
0
N/A
N/A
N/A
BYTE 3
BIT 0 1 2 3 DESCRIPTION/FUNCTION PCIF0 output enabled PCIF1 output enabled PCIF2 output enabled allow control of PCIF0 with assertion of PCI_Stop 0 = free running 1 = stopped with PCI_Stop allow control of PCIF1 with assertion of PCI_Stop 0 = free running 1 = stopped with PCI_Stop allow control of PCIF2 with assertion of PCI_Stop 0 = free running 1 = stopped with PCI_Stop USB 48MHz output enabled DOT 48 MHz output enabled TYPE RW RW RW RW POWER UP CONDITION 1 = enabled 1 = enabled 1 = enabled 0 = free running not affected by PCI_Stop 0 = free running not affected by PCI_Stop 0 = free running not affected by PCI_Stop 1 = enabled 1 = enabled OUTPUT(S) AFFECTED PCIF0 PCIF1 PCIF2 PCIF0 PIN AFFECTED 5 6 7 5 SOURCE PIN N/A N/A N/A N/A
4
RW
PCIF1
6
N/A
5
RW
PCIF2
7
N/A
6 7
RW RW
USB 48MHz DOT 48MHz
39 38
N/A N/A
2001 Sep 07
19
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
BYTE 4
BIT 0 DESCRIPTION/FUNCTION 66Buff0/3V66_2 output enabled 1 = enabled 0 = disabled 66Buff1/3V66_3 output enabled 1 = enabled 0 = disabled 66Buff2/3V66_4 output enabled 1 = enabled 0 = disabled 3V66_5 output enabled 1 = enabled 0 = disabled 3V66_1/VCH output enabled 1 = enabled 0 = disabled 3V66_0 output enabled 1 = enabled 0 = disabled not used not used TYPE RW POWER UP CONDITION 1 = enabled OUTPUT(S) AFFECTED 66Buff0/3V66_2 PIN NUMBER 21
1
RW
1 = enabled
66Buff1/3V66_3
22
2
RW
1 = enabled
66Buff2/3V66_4
23
3
RW
1 = enabled
3V66_5
24
4
RW
1 = enabled
3V66_1/VCH
35
5
RW
1 = enabled
3V66_0
33
6 7
-- --
0 0
-- --
-- --
BYTE 5
BIT 0 1 2 3 4 5 6 7 DOT edge rate control not used not used not used not used USB edge rate control DESCRIPTION/FUNCTION TYPE RW RW RW RW -- -- -- -- POWER UP CONDITION 0 0 0 0 0 0 0 0 OUTPUT(S) AFFECTED USB USB DOT DOT -- -- -- -- PIN NUMBER 39 39 38 38 -- -- -- --
BYTE 6
BIT 0 1 2 3 4 5 6 7 DESCRIPTION/FUNCTION vendor ID bit 0 vendor ID bit 1 vendor ID bit 2 vendor ID bit 3 revision code bit 0 revision code bit 1 revision code bit 2 revision code bit 3 TYPE R R R R R R R R POWER UP CONDITION 1 1 1 0 0 0 0 0 OUTPUT(S) AFFECTED N/A N/A N/A N/A N/A N/A N/A N/A PIN NUMBER N/A N/A N/A N/A N/A N/A N/A N/A
2001 Sep 07
20
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
APPLICATION NOTES
Optimum performance of the PCK2023 can only be achieved through correct implementation in the system board. This application note addresses many of the issues associated with integrating the PCK2023 on a system board. Descriptions for circuit board layout and decoupling are provided in this application note.
The components associated with the clocks should be placed on the same layer as the PCK2023 IC. This will allow the layout to avoid the use of vias for interconnect, thereby reducing node capacitance and trace inductance. All components should be placed as close to the IC as possible.
Circuit board layout
It is possible to generate a circuit board with the proper characteristics using four-layer configuration. Figure 11 shows the layer stack-up. It is critical to keep the clock signals on a plane next to a ground plane to ensure they are ground referenced otherwise the clock signals may experience significant distortion and added jitter. Static signals (such as SPREAD, PWRDWN, etc.) can be placed on a layer next to the power plane.
CLOCK SIGNALS
GROUND
POWER
STATIC SIGNALS
SW00857
Figure 11. Optimum board layout
2001 Sep 07
21
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
Component decoupling
Decoupling is another important consideration to ensure optimum operation of the PCK2023. A first pass decoupling capacitor value may be determined by applying the following equation: C bypass + 1 where 2pF pswX max
capacitor manufacture's datasheet to determine the optimum material type to use. Additional filtering on the Analog supplies (AVDD) may be used to reduce the noise coupled from the circuit board global VDD to the internal VDD of the PCK2023. One way to do this is to use a PI filter. The specific values should be selected to allow proper decoupling on the pin side while rejecting the digital switching noise. A spectrum analyzer can provide considerable insight to ensure optimum values are selected. Measure the frequency content of the supply on either side of the inductor to verify the values selected reduce the noise on the component side of the filter. To provide the maximum isolation, each AVDD line should have a separate filter since the internal circuitry using these lines have very different switching requirements. In general, pin 25 is strictly a static current draw and should not have any switching noise. Great care has been taken to reduce the sensitivity to supply noise, but there is a finite limit to the capability to do this, therefore added filtering on the board should enhance performance. Pin 46 is used as a supply to the internal PLLs. This node will contain some high frequency switching noise since the internal PLLs operate up to 200 MHz. Again, additional filtering will improve the performance of the part. If a single filter is used for both supplies, noise from the PLL supply (pin 46) can couple int the Iref supply (pin 25) and increase the jitter of the HOST outputs.
X max + DV DI F psw + X max 2pL psw
V is the maximum supply noise permitted (20 mV, for example) I is the maximum current draw for the clock Lpsw is the power supply lead inductance Fpsw is the frequency below which the power supply wiring is adequate The maximum current may be determined by considering the switching of the clock outputs and the capacitive load on these outputs. The following equation may be used to determine the current per output. Once the current for each clock output is determined, they can be summed to determine the total switching current.
i + C load dV dt
Most of these values can be determined from the usage in the board design. For example, the IOCLK has a specified edge rate of 1.25 ns typical when slewing between 0.7 and 2.4 volts and the maximum Cload is 30 pF. The HOST outputs are a special case since, although the output either drives current or is off, only one drives at a time, so the current is really steered rather than switched. The act of steering the current reduces switching noise on these supplies, therefore the HOST supplies require less decoupling. As a starting point, assume the supply current for each HOST output is equal to 1/2 the programmed output current. Decoupling capacitors should be located as close to the power pins on the IC as possible. The use of too much decoupling should be avoided since it could cause oscillations on the part because of the LC circuit (the IC leads act as inductors). Also, it is possible to cause oscillations from resonance between the board inductance and board capacitance. Two capacitors may be placed in parallel to effectively extend the capacitance range of the decoupling since the larger capacitor will have a self-resonance at a lower frequency than the smaller capacitor. When using this method, the split between values should be 100 (i.e., 0.1 F and 0.001 F). Another consideration when selecting the decoupling capacitors is the dielectric material of the capacitor. This will depend on the frequency range of concern. For lower frequencies, Z5U material may be used since this type of capacitor has a self-resonance in the 1 MHz to 20 MHz range. Capacitors of NPO have a self-resonance much higher and are more for high frequency decoupling. Consult a
AVDD
VDD3.3
SW00858
Figure 12. PI filter for all analog VDD lines
Iref decoupling
Filtering on the Iref supply has already been discussed, but additional filtering can be added on the Iref pin (pin 26) to perform additional filtering of the reference current. This reference current is critical to the performance of the HOST outputs since variation in this current is directly proportional to jitter on the HOST outputs. On-die decoupling has been included to reduce noise on this node, but additional decoupling could also be used to further reduce any noise. Care must be taken with this approach to ensure the capacitor and reference resistor share the same ground. Placing both components side by side is an optimum configuration. This external capacitor should not exceed TBD pF to ensure the current source inside the PCK2023 can supply enough charge for this node to reach reference value (1.1 volt).
2001 Sep 07
22
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
Functional connection
Figure 13 shows a partial diagram of the PCK2023 in an application. The host outputs are differential current drivers, therefore the output current is converted to a voltage by using some type of load resistor (in this case, RS and RP). The output current is based on two, the value of Rref and the setting on MULTSEL0 and MULTSEL1 pins. The Iref pin is actually a reference voltage which is fixed at 1.1 volts, therefore, Iref is 1.1/Rref. There are limitations on how large the current can be made. This is coupled to the termination resistors used. The maximum voltage which should be observed at the HOST or HOST pins of the PCK2023 is 1.1 volts. This value may be determined by using:
V max + (R s ) R P)N mult 1.1 R ref
where RS and RP are the termination resistor values, Nmult is the current multiplier set by MULTSEL0 and MULTSEL1, and Rref is the current reference resistor. Vmax should not exceed 1.1 volts because of the internal current source configuration.
RS HCLK RS HCLKB HI HI
RP
RP
LOAD
Iref
Rref
PCK2023
SW00859
Figure 13. PCK2023 implementation in a circuit board
2001 Sep 07
23
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
S1 VDD 2RT
CL
500
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT
SW00574
Figure 14. Host clock measurements
TPERIOD DUTY CYCLE THIGH 2.5 V CLOCKING INTERFACE 2.0 V 1.25 V 0.4 V TLOW TRISE TFALL TPERIOD DUTY CYCLE THIGH 3.3 V CLOCKING INTERFACE (TTL) 2.4 V 1.5 V 0.4 V TLOW TRISE TFALL
SW00860
Figure 15. 2.5 V/3.3 V clock waveforms
2001 Sep 07
24
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
AC WAVEFORMS
VM = 1.25 V @ VDDL and 1.5 V @ VDD3 VX = VOL + 0.3 V VY = VOH - 0.3 V VOL and VOH are the typical output voltage drop that occur with the output load.
VI SEL1, SEL0 GND tPLZ VDD tPZL VM
VDDQ2 CPUCLK @133MHz 1.25V VSS
OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ
VM VX tPZH
VDDQ3 3v66 @66MHz 1.5V VSS CPU leads 3V66 THPOFFSET
VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VSS Outputs enabled VY VM
Outputs disabled
Outputs enabled
SW00569
SW00571
Figure 16. Host clock
Figure 18. State enable and disable times
COMPONENT MEASUREMENT POINTS
2.5VOLT MEASURE POINTS VOH = 2.0V VDDQ2 VIH = 1.7V 1.25V VIL = 0.7V SYSTEM MEASUREMENT POINTS 3.3VOLT MEASURE POINTS VOH = 2.4V VDDQ3 VIH = 2.0V 1.5V VIL = 0.7V SYSTEM MEASUREMENT POINTS
VOL = 0.4V VSS COMPONENT MEASUREMENT POINTS
VOL = 0.4V VSS
SW00570
Figure 17. 3.3 V clock waveforms
2001 Sep 07
25
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
S1 VDD 2RT
CL
500
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT CL includes jig and probe capacitance Figure 19. Load circuitry for switching times
SW00572
PWRDWN
CPUCLK (INTERNAL)
PCICLK (INTERNAL)
PWRDWN
CPUCLK (EXTERNAL) PCICLK (EXTERNAL)
USB (48 MHz)
Figure 20. Power management
2001 Sep 07
26
AA AA AA AA
OSC & VCO
SW00573
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
2001 Sep 07
27
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
2001 Sep 07
28
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
NOTES
2001 Sep 07
29
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator
PCK2023
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Date of release: 09-01
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 09142
Philips Semiconductors
2001 Sep 07 30

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